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HARDWARE - Intel Itanium 2

INTEL ITANIUM MICROPROCESSOR PHOTOS 2

PHOTO Microprocessor Intel Itanium 2

MOTHER TO Microprocessor Intel Itanium 2

SOCKET CAP 418

PHOTO SOCKET CAP 611

Microprocessor Intel Itanium 2
Mother Board for Microprocessor Intel Itanium Intel Itanium 2
/ Core Intel Itanium 2

No. pin, bus, and voltage multiplied
L1/L2/L3 Cache Socket


Transistors-733 MMX SSE Itanium (Merced) July, 2001
pines733MHz 418 (133x5.5) (64-bit Bus dualpumped)? v
PAC418
16KB data (4-way) 16KB instruction (4-way) 96KB L2 unified or integrated (6-way) 2MB unified L3 o4MB (4-way) * 16TB millones0.18μm cacheable
25 ~ 300mm ² wide area? million L3 {? microns -? mm ²} (2MB) 295 000 000 L3 {? microns -? mm ²} (4MB)
-800 MMX SSE Itanium (Merced) July, 2001
pines800MHz 418 (133x6.0) (64-bit Bus dualpumped)? v
PAC418
16KB data (4-way) 16KB instruction (4-way) 96KB Integrated unified L2 (6-way) 2MB unified L3 o4MB (4-way) * 16TB millones0.18μm cacheable
25 ~ 300mm ² wide area? million L3 {? microns -? mm ²} (2MB) 295 000 000 L3 {? microns -? mm ²} (4MB) 200-900
MMX SSE
Itanium (McKinley) July 8, 2002 - {$ 1338} (1.5MB) 611
pines900MHz (200x4.5) (128-bit dual-pumped bus)? v
PAC611
datos16KB instrucciones256KB 16KB unified L2 on-Area integrada1.5MB unified L3 *?
221 GB cacheable millones0.18μm
ancho463mm ² area Itanium 2-1.0G MMX SSE (McKinley) July 8, 2002 - {$?} (1.5MB) July 8, 2002 - {$ 4226} (3MB)
pines1000MHz 611 (200x5.0) (128-bit dual-pumped bus)? v
PAC611
16KB datos16KB instrucciones256KB unified L2 on-field integrada1.5MB o3MB unified L3 *? 221 GB cacheable
millones0.18μm ancho463mm ²

Itanium 2-1.3G MMX SSE (Madison) - Coppe chipJunio 30, 2003 - {$ 1338}
pines1300MHz 611 (200x6.5) (128-bit dual-pumped bus)? v
PAC611
16KB datos16KB instrucciones256KB unified L2 on-field integrada3MB unified L3 *? ~ 500 GB cacheable
millones0.13μm width? mm ²
Itanium 2-1.4G MMX SSE (Madison) - Coppe chipJunio \u200b\u200b30, 2003 - {$ 2247}
pines1400MHz 611 (200x7.0) (128-bit dual-pumped bus)? v
PAC611
16KB datos16KB instrucciones256KB L2 unified on-Area integrada4MB unified L3 *?
~ 500 GB cacheable millones0.13μm wide? mm ² area
Itanium 2-1.5G MMX SSE (Madison) - copper chipJunio \u200b\u200b30, 2003 - {$ 3692} (6MB) November 2004 (4MB )
pines1500MHz 611 (200x7.5) (128-bit dual-pumped bus)? v
PAC611
datos16KB instrucciones256KB 16KB unified L2 on-Area integrada4MB o6MB unified L3 *?
~ 500 GB cacheable millones0.13μm wide? mm ² area

Itanium 2-1.6G MMX SSE (Madison 9M) November, 2004
pines1600MHz 611 (200x8.0) (128-bit dual-pumped bus)? v
PAC611
datos16KB instrucciones256KB 16KB unified L2 on-Area integrada6MB o9MB unified L3 * ? GB cacheable
? million? microns wide? mm ² area
Itanium 2-1.66G MMX SSE (Madison 9M) July, 2005
pines1666MHz 611 (333x5.0) (128-bit dual-pumped bus)? v
PAC611
datos16KB 16KB L2 unified instrucciones256KB integrada6MB On-area o9MB unified L3 *? GB cacheable
? million? microns wide? mm ² area

LV Itanium 2-1.0G MMX SSE (Deerfield) September 8, 2003 - {$ 744} 611
pines1000MHz (200x5.0) (128-bit dual-pumped bus)? v

PAC611 instrucciones256KB datos16KB 16KB L2 unified on-Area integrada1.5MB unified L3 *? GB cacheable
? millones0.13μm wide? mm ² area
LV Itanium 2-1.3G MMX SSE (Deerfield) November, 2004
pines1300MHz 611 (200x6.5) (128-bit dual-pumped bus)? V
PAC611
datos16KB instrucciones256KB 16KB L2 unified on-Area integrada3MB unified L3 *? GB cacheable
? millones0.13μm wide? mm ² area
Itanium 2-1.4G MMX SSE (Deerfield) September 8, 2003 - {$ 1172} (1.5MB) April 13, 2004 - {$ 1172} (3MB)
pines1400MHz 611 (200x7.0) ( 128-bit dual-pumped bus)? v
PAC611
datos16KB instrucciones256KB 16KB unified L2 on-Area integrada1.5MB o3MB unified L3 *? GB cacheable
? millones0.13μm wide? mm ² area
Itanium 2-1.6G MMX SSE (Deerfield) May, 2004 - {$ 2408}
pines1600MHz 611 (200x8.0) (128-bit dual-pumped bus)? v PAC611

datos16KB instrucciones256KB 16KB unified L2 on-Area integrada3MB unified L3 *? GB cacheable
? millones0.13μm wide? mm ² area
Itanium 2-1.6G MMX SSE (Deerfield) November, 2004 - {$ 2408}
pines1600MHz 611 (266x6.0) (128-bit dual-pumped bus)? v
PAC611
datos16KB instrucciones256KB 16KB unified L2 on-Area integrada3MB unified L3 *? GB cacheable
? millones0.13μm wide? mm ² area
Itanium
2-9010 MMX SSE (Montecito) (Hyperthreading) 2006?
pines1600MHz 611 (200x8.0) (128-bit dual-pumped bus)? V
PAC611
? KB data? Instrucciones1MB KB unified L2 on-Area integrada6MB unified L3 *? GB cacheable
1720 millones0.09μm ancho? Mm ² area
Itanium 2-9020 MMX SSE (Montecito) (dual coe, Hyperthreading) 2006?
pines1400MHz 611 (200x7.0) (128-bit dual-pumped bus)? V
PAC611
2x? KB datos2x? KB instrucciones2x integrada2x unified 1MB L2 9MB L3 on-unified * Area? GB cacheable
1720 millones0.09μm ancho? mm ² area
Itanium 2-9040 MMX SSE (Montecito) (dual coe, Hyperthreading) 2006?
pines1600MHz 611 (266x6.0) (128-bit dual-pumped bus)? V
PAC611
2x? KB datos2x? KB instrucciones2x integrada2x unified 1MB L2 9MB L3 on-unified * Area? GB cacheable
1720 millones0.09μm ancho? mm ² area
Itanium 2 -?? MMX SSE (Montecito) (dual coe, Hyperthreading) 2006?
611 pin? MHz ("X") (128-bit dual-pumped bus)? V
PAC611
2x? KB datos2x? KB instrucciones2x integrada2x unified 1MB L2 12MB L3 unified on-Area *? GB cacheable
millones0.09μm 1720 wide? mm ² area

Itanium 2 -?? MMX SSE (Fanwood - 2-way) (dual coe, Hyperthreading) 2006?
? pin? MHz ("X") (128-bit dual-pumped bus)? v
?
2x? KB datos2x? KB instrucciones2x? MB L2 unified integrada2x? MB L3 on-Unified Area *? GB cacheable
? million? microns wide? mm ² area

Itanium 2 -?? MMX SSE (Millington - 2-way) (dual coe, Hyperthreading) 2006?
? pin? MHz ("X") (128-bit dual-pumped bus)? v
?
2x? KB datos2x? KB instrucciones2x? MB L2 unified integrada2x? MB L3 on-Unified Area *? GB cacheable
? million? microns wide? mm ² area

Itanium 2 -?? MMX SSE (Shavano) (Hyperthreading) 2006?
? pin? MHz ("X") (128-bit dual-pumped bus)? v
?
? KB data? KB instructions? MB L2 unified or integrated? MB L3 on-Unified Area *? GB cacheable
? million? microns wide? mm ² area

Itanium 2 -?? MMX SSE (Montvale) (dual coe, Hyperthreading) 2006?
? pin? MHz ("X") (128-bit dual-pumped bus)? v
?
2x? KB datos2x? Instrucciones2x KB L2 unified 1MB-12MB on integrada2x Area unified L3 *?
GB cacheable? millones0.065μm ancho? mm ² area
Itanium
3 -?? MMX SSE (Tukwila) (multi coe, Hyperthreading) 2006?
? pines? MHz (-x ?)(?- bit?-pumped bus)? v
?
4x? KB datos4x? KB instrucciones4x? MB L2 unified integrada4x? MB L3 on-unified * Area?
GB cacheable? millones0.065μm ancho? mm ² area
Itanium
3 -?? MMX SSE (Dimona) (dual coe, Hyperthreading) 2006?
? pines? MHz (-x ?)(?- bit?-pumped bus)? v
?
2x? KB datos2x? KB instrucciones2x? MB L2 Unified integrada2x? MB L3 on-Unified Area *? GB cacheable
? million? microns wide? mm ² area
Itanium
3 -?? MMX SSE (Poulson) (multi coe, Hyperthreading) 2006?
? pin? MHz (? x ?)(?- bit?-pumped bus)? v
?
4x? KB datos4x? KB instrucciones4x? MB integrated L2 unified
? million? microns wide? mm ² area

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