Tuesday, May 12, 2009

Gpsphone Pokemon Emerald

HARDWARE - Intel Core 2 Extreme quad-core


PHOTOS
INTEL CORE 2 EXTREME


CORE FOUR








The Intel ® Core ™ 2 Extreme Quad-Core is the first processor in its class for desktop and offers the most advanced processors. This processor is designed for computer enthusiasts.

Current multimedia applications, such as editing and playback of video / audio and 3D modeling, leverage multi-threaded computing for high performance and demonstrate an extraordinary scalability with quad-core processors. The Intel Core 2 Extreme Quad-Core can perform several tasks same time a significant improvement in terms of system responsiveness when downloading certain tasks to specific cores to the processor release additional resources for other tasks and enable customers to do more in less time.
The Intel ® 975X Express Chipset supports the Intel Core 2 Extreme Quad-Core. This combination of processor and chipset offers an exciting range of options, including dual graphics, and provides an impressive level of performance for demanding users.
processor features Intel ® Core ™ 2 Extreme quad-core

features four processing equipment
core provides four independent cores
in a single package with 8 MB of L2 cache and a system bus to 1,066 MHz Four dedicated physical threads help operating systems and applications deliver additional performance, so end users can enjoy an improved ability to multitasking and multithreading with any type of application and workload.
Intel ® Wide Dynamic Execution Improves
speed and efficiency of execution, delivering more instructions per clock cycle. Each core can complete up to four full instructions simultaneously.
Access Intel ® Smart Memory
optimizes the use of bandwidth of data from the memory subsystem to accelerate order execution. A predictor of new design reduces the time the instructions have to wait to receive the data. The new search algorithm after transferring data from system memory to the fast L2 cache before execution. These functions keep the pipeline filled to improve processing capacity and performance. Intel ® Smart Cache
avanzada1
dynamically allocates the shared L2 cache to each processor core based on workload. The effective implementation of dual-core optimized increases the probability that each core can access data stored in the fast L2 cache, significantly reducing latency to access data that are used frequently and improve performance.
Intel ® Advanced Digital Media Boost Accelerates the execution
Streaming SIMD Extension (SSE) to significantly improve performance when using a wide range of applications including video, audio, imaging and photography, multimedia, encryption, financial, engineering and science. The 128-bit SSE instructions are now issued at a rate of one per clock cycle, multiplying in fact two execution speed compared to processors previous generation.
Intel ® Virtualization Technology (Intel ® VT) 2
With this technology, a single hardware platform to function as multiple "virtual" platforms. Intel VT improves manageability, limiting downtime and maintaining worker productivity by isolating computing activities into separate partitions. Intel ® 643

allows the processor to access larger amounts of memory. With appropriate hardware and 64-bit software, platforms based on an Intel processor supporting Intel 64 may allow the use of extended virtual and physical memory.
ejecución4 Disable Bit
Provides enhanced protection against the virus when implanted with a supporting operating system. Memory can be marked as executable or non executable, the processor sends an error message that the operating system if malicious code attempts to run on non-executable memory. This system prevents infection by this code.
Intel Designed Thermal Solution for Boxed Processors Includes
4-pin connector to control the fan speed to reduce noise when the fan runs more velocidad5. Technology control the fan speed is based on actual CPU temperature and power consumption. †
Warning: If you alter the clock frequency and / or stress, (1) could reduce system stability and useful life of the system and processor, (2) the processor and other system components may be damaged, (3) could reduce system performance, (4) could result in additional damage (5) could be affected the integrity of system data. Intel has not tested and does not warrant the operation of the processor beyond its specifications.
1 For the Intel ® Core ™ 2 Extreme quad-core, shared L2 cache refers to 4 MB of L2 cache per pair of nuclei, which gives resulting in a total of 8 MB of L2 cache.
2 The Intel ® Virtualization Technology requires a computer system with an enabled Intel ® processor, BIOS, virtual machine monitor (VMM) and for some uses, certain platform software developed for this technology. Functionality, performance or other benefits will vary depending on your hardware and software, and may require an updated BIOS. Software applications may not be compatible with all operating systems. Ask your provider for details of applications.
3 The 64-bit computing on Intel architecture requires a computer system with a processor, chipset, BIOS, operating system, device drivers and applications enabled for Intel ® 64 architecture. Processors will not operate, even in 32 bit mode without an architecture-enabled BIOS Intel ® 64. Performance will vary depending on configurations of hardware and software. Check with your system vendor for more information.
4 To activate the functionality of the Execute Disable bit requires a PC with a processor capability and a supporting operating system. Ask your PC manufacturer on whether your system delivers the functionality of Execute Disable Bit.
5 The acoustic benefits of the 4-pin header depend on the proper design of the motherboard. The manufacturer of your motherboard can give you more information on compatibility.
* Other brands and product names may be claimed as property of others.







Horny Hotmail Addresses

HARDWARE - Quad-Core AMD CHIPS



PHOTOS OF "DUAL CORE"
OF AMD





CHIPS "AMD" CORE FOUR



The Quad-Core AMD Opteron meet today's demanding data centers Bill Laing, general manager of the Windows Server Division at Microsoft.
AMD has finally introduced the AMD Opteron (formerly known as Barcelona), the first microprocessor native x86 quad-core. This is the company's bid to counter the influence of market Intel Xeon servers and development environments. As a novelty, highlight the Direct Connect Architecture, developed by AMD itself, which innovates in key areas such as energy efficiency, increased performance of the processes of virtualization and investment protection via a customer-centric approach that allows a transition fluid from the dual core to quad with the same components and thermal energy to help reduce costs infraestructura.En Currently there are over 50 options available system based on the AMD Quad-core Opteron from major manufacturers and integrators such as Dell, HP, Oracle, Fujitsu, Gateway, Verari and Citrix, among others. Bill Laing, general manager of the Windows Server Division of Microsoft points out, for example, that "multi-core technology 64-bit Direct Connect Architecture and integrated virtualization, AMD Opteron processors provide users of Microsoft Windows an innovative platform. " In his view, if the Windows Server 2008, SQL 2008 and Visual Studio 2008 running on Quad-Core AMD Opteron, will provide "a platform for developing and implementing dynamic expedite appeal customers' IT environments. "AMD Opteron quad-core Direct Connect Architecture excel in virtualized environments, due to the integrated memory controller, which offers a lower memory latency, and Rapid Virtualization Indexing, an innovation over AMD AMD Virtualization technology designed to reduce the overhead associated with virtualization strategy software.La AMD's common core allows customers to scale with one AMD architecture to reduce the complexity of managing the platform and increase uptime and the data center productivity.


AMD PHENOM X 4



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Friday, May 8, 2009

Prom Dressfinder By Size

HARDWARE - MICROPROCESSOR INTEL XEON SOCKET 603/604



XEON MICROPROCESSOR PHOTOS - SOCKET 603 to 604








INTEL CORE




SOCKET 603




SOCKET 604



"AS DESCRIBED EACH XEON MICROPROCESSOR"
AMOUNT PINES - BUS - MULTIPLIER -
VOLTAGE TYPE SOCKET CACHE MEMORY
L1/L2/L3
number of transistors




Xeon-1.4G


MMX SSE SSE2
(Foster) May 21, 2001 - {$ 268} 603
pines1400MHz (100x14) (64-bit Bus quadpumped) 1.7v Socket 603

8KB data (4-way) 12k μoperaciones (8-way) 256KB unified L2 integrated (8-way) * 4GB cacheable
42 millones0.18μm ancho217mm ² area

Xeon-1.5G


MMX SSE SSE2
(Foster) May 21, 2001 - {$ 309} 603
pines1500MHz (100x15) (64-bit Bus quadpumped) Socket 603 1.7v

8KB data (4-way) 12k μoperaciones (8-way ) integrated unified 256KB L2 (8-way) * 4GB cacheable
42 millones0.18μm ancho217mm ² area

Xeon-1.7G


MMX SSE SSE2 (Foster) May 21, 2001 - {$ 406} 603
pines1700MHz (100x17) (64-bit Bus quadpumped) Socket 603 1.7v

8KB data (4-way) 12k μoperaciones (8-way) 256KB L2 integrated unified (8-way) * 4GB cacheable
42 millones0.18μm ancho217mm ² area

Xeon-2.0G MMX SSE SSE2

(Foster) September 25, 2001 - {$ 615} 603
pines2000MHz (100x20) ( quadpumped 64-bit bus) 1.7v Socket 603

8KB data (4-way) 12k μoperaciones (8-way) 256KB unified L2 integrated (8-way) * 4GB cacheable
42 millones0.18μm ancho217mm ² area

LV Xeon-1.6G MMX SSE

SSE2 (Prestonia) (Hyperthreading) September 3, 2002 - {$ 355} 604
pines1600MHz (100x16) (64-bit Bus quadpumped) Socket 604 1.3v

8KB data (4 -way) 12k μoperaciones (8-way) 512KB unified L2 integrated (8-way) * 64GB cacheable
55 millones0.13μm ancho146mm ² area

Xeon-1.8G


MMX SSE SSE2
(Prestonia ) (Hyperthreading) February 25, 2002 - {$ 251} 603
pines1800MHz (100x18) (64-bit Bus quadpumped) Socket 603 1.5v

8KB data (4-way) 12k μoperaciones (8-way) 512KB L2 integrated unified (8-way) * 64GB cacheable
55 millones0.13μm ancho146mm ² area


Xeon-2.0A MMX SSE

SSE2 (Prestonia) (Hyperthreading) February 25, 2002 - {$ 417} 603
pines2000MHz (100x20) (64-bit Bus quadpumped) Socket 603 1.5v

8KB data (4-way) 12k μoperaciones (8-way) 512KB unified L2 integrated (8-way) * 64GB cacheable
55 millones0.13μm ancho146mm ² area


Xeon LV

-2.0A MMX SSE SSE2
(Prestonia) (Hyperthreading) April, 2003
pines2000MHz 604 (100x20) (64-bit Bus quadpumped) 1.3v Socket 604

8KB data (4-way) 12k μoperaciones (8-way) 512KB unified L2 integrated (8-way) * 64GB cacheable
55 millones0.13μm ancho146mm ² area


Xeon-2.0B


MMX SSE SSE2 (Prestonia) (Hyperthreading) November 18, 2002 - {$ 198} 604
pines2000MHz (133x15) (64-bit Bus quadpumped) Socket 604 1.5v

8KB data (4-way) 12k μoperaciones (8-way ) integrated unified 512KB L2 (8-way) * 64GB cacheable
55 millones0.13μm ancho146mm ² area


Xeon-2.2G MMX SSE

SSE2 (Prestonia) (Hyperthreading) February 25, 2002 - {$ 615} 603
pines2200MHz (100x22) (64-bit Bus quadpumped) Socket 603 1.5v

8KB data (4-way) 12k μoperaciones (8-way) 512KB unified L2 integrated (8-way) * 64GB cacheable
55 millones0.13μm ancho146mm ² area


Xeon-2.4G


MMX SSE SSE2
(Prestonia) (Hyperthreading) April 23, 2002 - {$ 615} 603
pines2400MHz (100x24 ) (64-bit Bus quadpumped) Socket 603 1.5v

8KB data (4-way) 12k μoperaciones (8-way) 512KB unified L2 integrated (8-way) * 64GB cacheable
55 millones0.13μm ancho131mm ²
area

Xeon-2.4G


MMX SSE SSE2
(Prestonia) (Hyperthreading) November 18, 2002 - {$ 234} 604
pines2400MHz (133x18) (64-bit Bus quadpumped) 1.5v Socket 604

8KB data (4-way) 12k μoperaciones (8-way) 512KB unified L2 integrated (8-way) * 64GB cacheable
55 millones0.13μm ancho131mm ² area

Xeon-2.6g


MMX SSE SSE2
(Prestonia) (Hyperthreading) September 11, 2002 - {$ 433} 603
pines2600MHz (100x26) (64-bit Bus quadpumped) 1.5v Socket
603
8KB data (4-way) 12k μoperaciones (8-way) 512KB unified L2 integrated (8-way) * 64GB cacheable
55 millones0.13μm ancho131mm ² area


Xeon-2.67G


MMX SSE SSE2
(Prestonia) (Hyperthreading) November 19, 2002 - {$ 337} 604
pines2666MHz (133x20) (64-bit Bus quadpumped) Socket 604 1.5v

8KB data (4-way) 12k μoperaciones ( 8-way) 512KB unified L2 integrated (8-way) * 64GB cacheable
55 millones0.13μm ancho131mm ² area



Xeon-2.8G


MMX SSE SSE2
(Prestonia) (Hyperthreading) September 11, 2002 - {$ 562} 603
pines2800MHz (100x28) (64-bit Bus quadpumped) Socket 603 1.5v

8KB data (4-way) 12k μoperaciones (8-way) 512KB unified L2 integrated (8-way) * 64GB cacheable
55 millones0.13μm ancho131mm ² area

Xeon-2.8G


MMX SSE SSE2
(Prestonia) (Hyperthreading ) November 18, 2002 - {$ 455} 604
pines2800MHz (133x21) (64-bit Bus quadpumped) Socket 604 1.5v

8KB data (4-way) 12k μoperaciones (8-way) 512KB Integrated unified L2 (8-way) * 64GB cacheable
55 millones0.13μm ancho131mm ² area


Xeon-3.06G


MMX SSE SSE2
(Prestonia) (Hyperthreading) February 3, 2003 - {$ 722} 604
pines3066MHz (133x23) (64-bit Bus quadpumped) Socket 604 1.5v

8KB data (4-way) 12k μoperaciones (8-way) 512KB unified L2 integrated (8-way) * 64GB cacheable
55 millones0.13μm ancho131mm ² area

Xeon-3.06G


MMX SSE SSE2
(Gallatin) (Hyperthreading) July 14, 2003 - {$ 690} 604
pines3066MHz (133x23) (64-bit Bus quadpumped) 1.525v
Socket 604
8KB data (4-way) 12k μoperaciones (8-way) 512KB unified L2 integrated (8-way) 1MB integrated L3 ( 8-way) * 64GB cacheable millones0.13μm
width 169 ~ 230mm ² area

Xeon-3.2G


MMX SSE SSE2
(Gallatin) (Hyperthreading) October 6, 2003 - {$ 851}
pines3200MHz 604 (133x24) (64-bit Bus quadpumped) 1.525v
Socket 604
8KB data (4-way) 12k μoperaciones (8-way) 512KB unified L2 integrated (8-way) 1MB integrated L3 (8-way) * 64GB cacheable
width 169 ~ 230mm ² millones0.13μm
area
Xeon 2.8G


MMX SSE SSE2 SSE3
(Nocona) (Hyperthreading, EM64T) July 28, 2004 - {$ 209} 604
pines2800MHz (200x14 ) (64-bit Bus quadpumped) 1.4V Socket 604

16KB data (8-way) 12k μoperaciones (8-way) 1MB L2 unified or integrated (8-way) * 64GB cacheable
125 millones0.09μm ancho112mm ² area
Xeon 3.0G



MMX SSE SSE2 SSE3
(Nocona) (Hyperthreading, EM64T) July 28, 2004 - {$ 316} 604 pines3000MHz
(200x15) (64-bit Bus quadpumped) 1.4V Socket 604

16KB data (8-way) 12k μoperaciones (8-way) 1MB L2 unified or integrated (8-way) * 64GB cacheable
125 millones0.09μm
ancho112mm ² area

Xeon 3.2G


MMX SSE SSE2 SSE3
(Nocona) (Hyperthreading, EM64T) July 28, 2004 - {$ 455} 604
pines3200MHz (200x16) (64-bit Bus quadpumped) 1.4V Socket 604

16KB data (8-way) 12k μoperaciones (8-way) 1MB L2 unified or integrated (8-way) * 64GB cacheable
125 millones0.09μm ancho112mm ² area

Xeon 3.4g


MMX SSE SSE2 SSE3
(Nocona) (Hyperthreading, EM64T) July 28, 2004 - {$ 690} 604
pines3400MHz (200x17) (64-bit Bus quadpumped)
1.4V Socket 604
16KB data (8-way) 12k μoperaciones (8-way) 1MB L2 unified or integrated (8-way) * 64GB cacheable
125 millones0.09μm ancho112mm ² area


Xeon 3.6g


MMX SSE SSE2 SSE3
(Nocona) (Hyperthreading, EM64T) July 28, 2004 - {$ 851} 604
pines3600MHz (200x18) (64-bit Bus quadpumped) 1.4V Socket 604

16KB data (8-way) 12k μoperaciones (8-way) 1MB L2 unified or integrated (8-way) * 64GB cacheable
125 millones0.09μm ancho112mm ² area


Xeon 3.8g


MMX SSE SSE2 SSE3
(Nocona) (Hyperthreading, EM64T) [not marketed]
pines3800MHz 604 (200x19) (64-bit Bus quadpumped) 1.4V Socket 604

16KB data (8-way) 12k μoperaciones (8-way) Integrated 1MB unified L2 (8-way) * 64GB cacheable
125 millones0.09μm ancho112mm ² area

Xeon 4.0g


MMX SSE SSE2 SSE3
(Nocona) (Hyperthreading, EM64T) [NO SALES DATA]
pines4000MHz 604 (200x20) (64-bit Bus quadpumped) 1.4V Socket 604

16KB data (8-way) 12k μoperaciones ( 8-way) 1MB L2 unified or integrated (8-way) * 64GB cacheable
125 millones0.09μm ancho112mm ² area

Xeon 2.8G MMX


SSE SSE2 SSE3
(Irwindale) (Hyperthreading, EM64T, NX bit) February 14, 2005
pines2800MHz 604 (200x14) (64-bit Bus quadpumped)? v
Socket 604
16KB data (8-way) 12k μoperaciones (8-way) 2MB integrated L2 unified (8-way) * Millones0.09μm 133 64GB cacheable
wide? Mm ² area


LV Xeon 3.0G


MMX SSE SSE2 SSE3
(Irwindale) (Hyperthreading, EM64T, NX bit) September 26, 2005 - {$ 519}
604 pines3000MHz (200x15) (Bus 64-bit quadpumped)? v
Socket 604
16KB data (8-way) 12k μoperaciones (8-way) 2MB L2 unified or integrated (8-way) * 64GB cacheable
133 millones0.09μm wide? mm ² area

Xeon 3.0G


MMX SSE SSE2 SSE3
(Irwindale) (Hyperthreading, EM64T, NX bit) February 14, 2005 - {$ 316}
604 pines3000MHz (200x15) (Bus 64-bit quadpumped)? V
Socket 604
16KB data (8-way) 12k μoperaciones (8-way) 2MB L2 unified or integrated (8 -way) * 64GB cacheable millones0.09μm
133 wide? mm ² area

3.2G Xeon MV


MMX SSE SSE2 SSE3
(Irwindale) (Hyperthreading, EM64T, NX bit) September 26 2005 - {$ 487}
604 pines3200MHz (200x16) (Bus 64-bit quadpumped)? v
Socket 604
16KB data (8-way) 12k μoperaciones (8-way) 2MB L2 unified or integrated (8-way) * 64GB cacheable
Millones0.09μm 133 wide? Mm ² area

Xeon 3.2G


MMX SSE SSE2 SSE3
(Irwindale) (Hyperthreading, EM64T, NX bit) February 14, 2005 - {$ 455} 604 pines3200MHz
(200x16) (64-bit Bus quadpumped)? v
Socket 604
16KB data (8-way) 12k μoperaciones (8-way) 2MB integrated L2 unified (8-way) * 64GB cacheable millones0.09μm
133 wide? mm ²
area

Xeon 3.4g


MMX SSE SSE2 SSE3
(Irwindale) (Hyperthreading, EM64T, NX bit) February 14, 2005 - {$ 690}
pines3400MHz 604 (200x17) (64-bit Bus quadpumped)? V
Socket 604
16KB data (8-way) 12k μoperaciones (8-way) 2MB integrated L2 unified (8-way) * 64GB cacheable millones0.09μm
133 wide? mm ² area

Xeon 3.6g


MMX SSE SSE2 SSE3 (Irwindale) (Hyperthreading, EM64T, NX bit) February 14, 2005 - {$ 851}
604 pines3600MHz (200x18) ( quadpumped 64-bit bus)? v
Socket 604
16KB data (8-way) 12k μoperaciones (8-way) 2MB integrated L2 unified (8-way) * 64GB cacheable millones0.09μm
133 wide? mm ² area

Xeon 3.8g


MMX SSE SSE2 SSE3
(Irwindale) (Hyperthreading, EM64T, NX bit) September 26, 2005 - {$ 851} 604
pines3800MHz (200x19) (64-bit Bus quadpumped)? v
Socket 604
16KB data (8-way) 12k μoperaciones (8-way) 2MB integrated L2 unified (8-way) * 64GB cacheable millones0.09μm
133 wide? mm ² area

Xeon DP-2.8 G


MMX SSE SSE2 SSE3
(Paxville DP) (dual coe, Hyperthreading, EM64T, NX bit) October 10, 2005 - {$ 1043}
pines2800MHz 604 (200x14) (Bus 64 quadpumped bits)? v

Socket 604 2x 16KB data (8-way) 2x 12k μoperaciones (8-way) 2x 2MB L2 unified or integrated (8-way) *?
230 GB cacheable millones0.09μm ancho206mm ² area

Xeon DP-


MMX SSE SSE2 SSE3
(Paxville DP) (dual coe, Hyperthreading, EM64T, NX bit) DIC. 604-pin
2006-MHz (166x?) (64-bit Bus quadpumped) v

Socket 604 2x 16KB data (8-way) 2x 12k μoperaciones (8-way) 2x 2MB L2 unified or integrated (8-way) *? 230 GB cacheable
millones0.09μm ancho206mm ² area

Xeon MP-1.4G


MMX SSE SSE2
(Foster MP) (Hyperthreading) March 12, 2002 - {$ 1177}
pines1400MHz 603 (100x14) (64-bit Bus quadpumped) Socket 603 1.7v

8KB data (4-way) 12k μoperaciones (8-way) 256KB unified L2 integrated (8-way) 512KB L3 (?-way) * 64GB cacheable millones0.18μm
108 wide? mm ² area
Xeon MP-
1.5G


MMX SSE SSE2
(Foster MP) (Hyperthreading) March 12, 2002 - {$ 1980}
pines1500MHz 603 (100x15) (64-bit Bus quadpumped) Socket 603 1.7v

8KB data (4-way) 12k μoperaciones (8-way) 256KB unified L2 integrated (8-way) 512KB L3 (?-Way) * 64GB cacheable millones0.18μm
108 wide? Mm ² area

Xeon MP-1.6G


MMX SSE SSE2
(Foster MP) (Hyperthreading) March 12, 2002 - {$ 3692}
pines1600MHz 603 (100x16) (64-bit Bus quadpumped) Socket 603 1.7v

8KB data (4 - way) 12k μoperaciones (8-way) 256KB unified L2 integrated (8-way) 1MB L3 (?-way) * 64GB cacheable millones0.18μm
108 wide? mm ² area

Xeon MP-1.7G


MMX SSE SSE2
(Foster MP) (Hyperthreading) [not marketed]
pines1700MHz 603 (100x17) (64-bit Bus quadpumped) Socket 603 1.7v

8KB data (4-way) 12k μoperaciones (8 -way) 256KB unified L2 integrated (8-way) 1MB L3 (?-way) * 64GB cacheable millones0.18μm
108 wide? mm ² area

Xeon MP-1.5G


MMX SSE SSE2
(Gallatin) (Hyperthreading) November 4, 2002 - {$ 1177}
pines1500MHz 603 (100x15) (64-bit Bus quadpumped) 1.475v
Socket 603
8KB data (4-way) 12k μoperaciones (8-way) 512KB Integrated unified L2 (8-way) 1MB integrated L3 (8-way) * 64GB cacheable millones0.13μm
width 169 ~ 230mm ² area

Xeon MP-1.9g


MMX SSE SSE2
( Gallatin) (Hyperthreading) November 4, 2002 - {$ 1980}
pines1900MHz 603 (100x19) (64-bit Bus quadpumped) 1.475v
Socket 603
8KB data (4-way) 12k μoperaciones (8-way) 512KB unified L2 integrated (8-way) 1MB integrated L3 (8-way) * 64GB cacheable millones0.13μm
width 169 ~ 230mm ² area

Xeon MP-2.0G

MMX SSE SSE2
(Gallatin) (Hyperthreading) June 30, 2003 - {$ 1177}
pines2000MHz 603 (100x20) (64-bit Bus quadpumped) 1.475v
Socket 603
8KB data (4-way) 12k μoperaciones (8 - way) 512KB unified L2 integrated (8-way) 1MB integrated L3 (8-way) * 64GB cacheable millones0.13μm
width 169 ~ 230mm ² area

Xeon MP-2.0G


MMX
SSE SSE2 (Gallatin) (Hyperthreading) November 4, 2002 - {$ 3692}
pines2000MHz 603 (100x20) (64-bit Bus quadpumped) 1.475v
Socket 603
8KB data (4-way) 12k μoperaciones (8-way) 512KB Integrated unified L2 (8-way) 2MB integrated L3 (8-way) * 64GB cacheable millones0.13μm
width 169 ~ 230mm ² area

Xeon MP-2.2G


MMX SSE SSE2
( Gallatin) (Hyperthreading) March 2, 2004 - {$ 1177}
pines2200MHz 603 (100x22) (64-bit Bus quadpumped) 1.475v
Socket 603
8KB data (4-way) 12k μoperaciones (8-way) 512KB unified L2 integrated (8-way) 2MB integrated L3 (8-way) * 64GB cacheable millones0.13μm
169 wide? mm ² area

Xeon MP-2.5G


MMX SSE SSE2 (Gallatin) (Hyperthreading) June 30, 2003 - {$ 1980}
pines2500MHz 603 (100x25) (64-bit Bus quadpumped) 1.475v
Socket 603
8KB data (4-way) 12k μoperaciones (8-way ) integrated unified 512KB L2 (8-way) 1MB integrated L3 (8-way) * 64GB cacheable millones0.13μm
width 169 ~ 230mm ² area

Xeon MP-2.7G


MMX SSE SSE2
(Gallatin) (Hyperthreading) March 2, 2004 - {$ 1980}
pines2700MHz 603 (100x27) (64-bit Bus quadpumped) 1.475v
Socket 603
8KB data (4-way) 12k μoperaciones (8-way) 512KB unified L2 integrated (8-way) 2MB integrated L3 (8-way) * 64GB cacheable millones0.13μm
169 wide? mm ² area

Xeon MP-2.8G


MMX SSE SSE2
(Gallatin) (Hyperthreading) June 30, 2003 - {$ 3692}
pines2800MHz 603 (100x28) (64-bit Bus quadpumped) 1.475v
Socket 603
8KB data (4-way) 12k μoperaciones (8-way) 512KB unified L2 integrated (8 -way) 2MB integrated L3 (8-way) * 64GB cacheable millones0.13μm
width 169 ~ 230mm ² area

Xeon MP-3.0G


MMX SSE SSE2 (Gallatin) (Hyperthreading) March 2, 2004 - {$ 3692}
pines3000MHz 603 (100x30) (64-bit Bus quadpumped) Socket 603 1.5v

8KB data (4-way) 12k μoperaciones (8-way) integrated unified 512KB L2 (8-way) 4MB integrated L3 (8-way) * 64GB cacheable millones0.13μm
169 wide? mm ² area

Xeon MP 3.16G


MMX SSE SSE2 SSE3
(Cranfod ) (Hyperthreading, EM64T, NX bit) March 29, 2005 - {$ 722} 604
pines3166MHz (166x19) (64-bit Bus quadpumped) 1.4V Socket 604

16KB data (?-way) 12k μoperaciones (8-way) 1MB unified L2 integrated (8-way) *? GB cacheable
? millones0.09μm wide? mm ² area

Xeon MP 3.66G


MMX SSE SSE2 SSE3
(Cranfod) (Hyperthreading, EM64T, NX bit) March 29, 2005 - {$ 963} 604 pines3666MHz
(166x22) (64-bit Bus quadpumped) 1.4V Socket 604

16KB data (?-way) 12k μoperaciones (8-way) 1MB L2 unified or integrated (8-way) *? GB cacheable
? millones0.09μm wide? mm ² area

Xeon MP 2.83G


MMX SSE SSE2 SSE3
(Potomac) (Hyperthreading, EM64T, NX bit) March 29, 2005 - {$ 1177}
pines2833MHz 604 (166x17) (64-bit Bus quadpumped) 1.3875v
Socket 604
16KB data (?-way) 12k μoperaciones (8-way) 1MB L2 unified or integrated (8 - way) 4MB integrated L3 (8-way) *? GB cacheable
? millones0.09μm wide? mm ² area

Xeon MP 3.0G


MMX SSE SSE2 SSE3
(Potomac) (Hyperthreading, EM64T, NX bit) March 29, 2005 - {$ 1980}
pines3000MHz 604 (166x18) (64-bit Bus quadpumped) 1.3875v
Socket 604
16KB data (?-way) 12k μoperaciones (8-way) 1MB L2 unified or integrated (8-way) 8MB Integrated L3 (8-way) *? GB cacheable
? millones0.09μm wide? mm ² area

Xeon MP 3.33G


MMX SSE SSE2 SSE3
(Potomac) (Hyperthreading, EM64T, NX bit) March 29, 2005 - $ 3,692 {604}
pines3333MHz (166x20) (64-bit Bus quadpumped) 1.3875v
Socket 604
16KB data (?-way) 12k μoperaciones (8-way) 1MB L2 unified or integrated (8-way) 8MB integrated L3 (8-way) *? GB
cacheable? millones0.09μm wide? mm ² area

Xeon MP 3.5G


MMX
SSE SSE2 SSE3 (Potomac) (Hyperthreading, EM64T, NX bit) 2006?
pines3500MHz 604 (166x21) (64-bit Bus quadpumped) 1.3875v
Socket 604
16KB data (?-Way) 12k μoperaciones (8-way) 1MB L2 unified or integrated (8-way) 8MB integrated L3 (8-way) *? GB cacheable
? millones0.09μm wide? mm ² area

Xeon 7020


MMX SSE SSE2 SSE3
(Paxville MP) (dual core, Hyperthreading, EM64T, NX bit) November 1, 2006 - $ 1,177 {604}
pines2666MHz (166x16) (64-bit Bus quadpumped)? v

Socket 604 2x 16KB data (8-way) 2x 12k μoperaciones (8-way) 2x Integrated 1MB unified L2 (8-way) *? GB cacheable
? millones0.09μm wide? mm ² area

Xeon 7030


MMX SSE SSE2 SSE3
(Paxville MP) (dual core, Hyperthreading, EM64T, NX bit) November 1, 2006 - {$ 1980}
pines2800MHz 604 (200x14) (64-bit Bus quadpumped)? v

Socket 604 2x 16KB data (8-way) 2x 12k μoperaciones (8-way) 2x 1MB L2 unified or integrated (8-way) *? GB cacheable
? millones0.09μm wide? mm ² area

Xeon 7040


MMX SSE SSE2 SSE3 (Paxville MP) (dual core, Hyperthreading, EM64T, NX bit) November 1, 2006 - {$ 3157}
604 pines3000MHz (166x18) (Bus 64-bit quadpumped)? V
Socket 604
2x 16KB data (8 - way) 2x 12k μoperaciones (8-way) 2x 2MB L2 unified or integrated (8-way) *? GB cacheable
? millones0.09μm wide? mm ² area

Xeon 7041


MMX SSE SSE2 SSE3
(Paxville MP) (dual core, Hyperthreading, EM64T, NX bit) November 1, 2006 - {$ 3157}
pines3000MHz 604 (200x15) (64-bit Bus quadpumped)? v

Socket 604 2x 16KB data (8-way) 2x 12k μoperaciones (8-way) 2x 2MB L2 unified or integrated (8-way) *? GB cacheable
? millones0.09μm wide? mm ² area

Xeon 7000 series


MMX SSE SSE2 SSE3
(Paxville MP) (dual core, Hyperthreading, EM64T, NX bit) Dec 2006?
604-pin? MHz (200x?) (64-bit Bus quadpumped)? V

Socket 604 2x 16KB data (8-way) 2x 12k μoperaciones (8-way) 2x 1MB L2 unified or integrated (8-way) *? GB cacheable
? millones0.09μm wide? mm ² area

Xeon 7110N


MMX SSE SSE2 SSE3
(Tulsa) (dual core, Hyperthreading, EM64T, NX bit) August 29, 2006 - {$ 856}
604 pines2500MHz (166x15) (Bus 64-bit quadpumped)? v
Socket 604
2x 16KB data (8-way) 2x 12k μoperaciones (8 - way) 2x 1MB L2 unified or integrated (8-way) 4MB on-area shared L3 (16-way) *? GB cacheable
1600 + millones0.065μm ancho435mm ² area

Xeon 7110M


MMX SSE SSE2 SSE3 (Tulsa) (dual core, Hyperthreading, EM64T, NX bit) August 29, 2006 - {$ 856}
604 pines2600MHz (200x13) (Bus 64-bit quadpumped)? v
Socket 604
2x 16KB data (8 -way) 2x 12k μoperaciones (8-way) 2x 1MB L2 unified or integrated (8-way) 4MB on-area shared L3 (16-way) *? GB cacheable
1600 + millones0.065μm ancho435mm ² area

Xeon 7120N


MMX SSE SSE2 SSE3 (Tulsa) (dual core, Hyperthreading, EM64T, NX bit) August 29, 2006 - {$ 1177}
604 pines3000MHz (166x18) (Bus 64-bit quadpumped)? v
Socket 604
2x 16KB data (8-way) 2x 12k μoperaciones (8-way) 2x 1MB L2 unified or integrated (8-way) 4MB on-area shared L3 (16-way) *? GB cacheable
1600 + millones0.065μm ancho435mm ² area

Xeon 7120M


MMX SSE SSE2 SSE3 (Tulsa) (dual core, Hyperthreading, EM64T, NX bit) August 29, 2006 - {$ 1177}
604 pines3000MHz (200x15) (Bus quadpumped 64 bits)? v

Socket 604 2x 16KB data (8-way) 2x 12k μoperaciones (8-way) 2x 1MB L2 unified or integrated (8-way) 4MB on-area shared L3 (16-way) *? GB 1600 + millones0.065μm
cacheable ancho435mm ² area

Xeon 7130N


MMX SSE SSE2 SSE3
(Tulsa) (dual core, Hyperthreading, EM64T, NX bit) August 29, 2006 - {$ 1391}
604 pines3166MHz (166x19) (Bus 64-bit quadpumped)? V
Socket 604
2x 16KB data (8-way) 2x 12k μoperaciones (8-way) 2x 1MB L2 unified or integrated (8 - way) 8MB on-area shared L3 (16-way) *? GB cacheable
1600 + millones0.065μm ancho435mm ² area

Xeon 7130M


MMX SSE SSE2 SSE3
(Tulsa) (dual core , Hyperthreading, EM64T, NX bit) August 29, 2006 - {$ 1391}
604 pines3200MHz (200x16) (Bus 64-bit quadpumped)? v
Socket 604
2x 16KB data (8-way) 2x 12k μoperaciones (8-way ) 2x 1MB L2 unified integrated (8-way) 8MB on-area shared L3 (16-way) *? GB cacheable
1600 + millones0.065μm ancho435mm ² area

Xeon 7140N


MMX SSE SSE2 SSE3
(Tulsa ) (dual core, Hyperthreading, EM64T, NX bit) August 29, 2006 - {$ 1980}
604 pines3333MHz (166x20) (Bus 64-bit quadpumped)? v
Socket 604
2x 16KB data (8-way) 2x 12k μoperaciones (8-way) 2x 1MB L2 unified or integrated (8-way) 16MB on-area shared L3 (16-way) *? GB cacheable
1600 + millones0.065μm ancho435mm ² area

Xeon 7140M


MMX SSE SSE2 SSE3 (Tulsa) (dual core, Hyperthreading, EM64T, NX bit) August 29, 2006 - {$ 1980}
604 pines3400MHz (200x17) (Bus 64-bit quadpumped)? V

Socket 604 2x 16KB data (8-way) 2x 12k μoperaciones (8-way) 2x 1MB L2 unified or integrated (8-way) 16MB on-area shared L3 (16-way) *? GB cacheable
millones0.065μm 1600 + ancho435mm ² area

Xeon Sossaman


MMX SSE SSE2 SSE3 (Sossaman) (dual core, Hyperthreading, EM64T, NX bit) 2006
604-pin? MHz (166x?) (Bus 64-bit quadpumped)? v
Socket 604
2x 16KB data (8-way) 2x 12k μoperaciones (8-way) 2x? MB L2 unified or integrated (8-way) *? GB cacheable
? millones0.065μm wide? mm ² area




WINDOWS VISTA TRICKS

Wednesday, May 6, 2009

Tingling After Cortisone Shot

HARDWARE - Intel Itanium 2

INTEL ITANIUM MICROPROCESSOR PHOTOS 2



PHOTO Microprocessor Intel Itanium 2

MOTHER TO Microprocessor Intel Itanium 2




SOCKET CAP 418



PHOTO SOCKET CAP 611



Microprocessor Intel Itanium 2
Mother Board for Microprocessor Intel Itanium Intel Itanium 2
/ Core Intel Itanium 2

No. pin, bus, and voltage multiplied
L1/L2/L3 Cache Socket


Transistors-733 MMX SSE Itanium (Merced) July, 2001
pines733MHz 418 (133x5.5) (64-bit Bus dualpumped)? v
PAC418
16KB data (4-way) 16KB instruction (4-way) 96KB L2 unified or integrated (6-way) 2MB unified L3 o4MB (4-way) * 16TB millones0.18μm cacheable
25 ~ 300mm ² wide area? million L3 {? microns -? mm ²} (2MB) 295 000 000 L3 {? microns -? mm ²} (4MB)
-800 MMX SSE Itanium (Merced) July, 2001
pines800MHz 418 (133x6.0) (64-bit Bus dualpumped)? v
PAC418
16KB data (4-way) 16KB instruction (4-way) 96KB Integrated unified L2 (6-way) 2MB unified L3 o4MB (4-way) * 16TB millones0.18μm cacheable
25 ~ 300mm ² wide area? million L3 {? microns -? mm ²} (2MB) 295 000 000 L3 {? microns -? mm ²} (4MB) 200-900
MMX SSE
Itanium (McKinley) July 8, 2002 - {$ 1338} (1.5MB) 611
pines900MHz (200x4.5) (128-bit dual-pumped bus)? v
PAC611
datos16KB instrucciones256KB 16KB unified L2 on-Area integrada1.5MB unified L3 *?
221 GB cacheable millones0.18μm
ancho463mm ² area Itanium 2-1.0G MMX SSE (McKinley) July 8, 2002 - {$?} (1.5MB) July 8, 2002 - {$ 4226} (3MB)
pines1000MHz 611 (200x5.0) (128-bit dual-pumped bus)? v
PAC611
16KB datos16KB instrucciones256KB unified L2 on-field integrada1.5MB o3MB unified L3 *? 221 GB cacheable
millones0.18μm ancho463mm ²

Itanium 2-1.3G MMX SSE (Madison) - Coppe chipJunio 30, 2003 - {$ 1338}
pines1300MHz 611 (200x6.5) (128-bit dual-pumped bus)? v
PAC611
16KB datos16KB instrucciones256KB unified L2 on-field integrada3MB unified L3 *? ~ 500 GB cacheable
millones0.13μm width? mm ²
Itanium 2-1.4G MMX SSE (Madison) - Coppe chipJunio \u200b\u200b30, 2003 - {$ 2247}
pines1400MHz 611 (200x7.0) (128-bit dual-pumped bus)? v
PAC611
16KB datos16KB instrucciones256KB L2 unified on-Area integrada4MB unified L3 *?
~ 500 GB cacheable millones0.13μm wide? mm ² area
Itanium 2-1.5G MMX SSE (Madison) - copper chipJunio \u200b\u200b30, 2003 - {$ 3692} (6MB) November 2004 (4MB )
pines1500MHz 611 (200x7.5) (128-bit dual-pumped bus)? v
PAC611
datos16KB instrucciones256KB 16KB unified L2 on-Area integrada4MB o6MB unified L3 *?
~ 500 GB cacheable millones0.13μm wide? mm ² area

Itanium 2-1.6G MMX SSE (Madison 9M) November, 2004
pines1600MHz 611 (200x8.0) (128-bit dual-pumped bus)? v
PAC611
datos16KB instrucciones256KB 16KB unified L2 on-Area integrada6MB o9MB unified L3 * ? GB cacheable
? million? microns wide? mm ² area
Itanium 2-1.66G MMX SSE (Madison 9M) July, 2005
pines1666MHz 611 (333x5.0) (128-bit dual-pumped bus)? v
PAC611
datos16KB 16KB L2 unified instrucciones256KB integrada6MB On-area o9MB unified L3 *? GB cacheable
? million? microns wide? mm ² area

LV Itanium 2-1.0G MMX SSE (Deerfield) September 8, 2003 - {$ 744} 611
pines1000MHz (200x5.0) (128-bit dual-pumped bus)? v

PAC611 instrucciones256KB datos16KB 16KB L2 unified on-Area integrada1.5MB unified L3 *? GB cacheable
? millones0.13μm wide? mm ² area
LV Itanium 2-1.3G MMX SSE (Deerfield) November, 2004
pines1300MHz 611 (200x6.5) (128-bit dual-pumped bus)? V
PAC611
datos16KB instrucciones256KB 16KB L2 unified on-Area integrada3MB unified L3 *? GB cacheable
? millones0.13μm wide? mm ² area
Itanium 2-1.4G MMX SSE (Deerfield) September 8, 2003 - {$ 1172} (1.5MB) April 13, 2004 - {$ 1172} (3MB)
pines1400MHz 611 (200x7.0) ( 128-bit dual-pumped bus)? v
PAC611
datos16KB instrucciones256KB 16KB unified L2 on-Area integrada1.5MB o3MB unified L3 *? GB cacheable
? millones0.13μm wide? mm ² area
Itanium 2-1.6G MMX SSE (Deerfield) May, 2004 - {$ 2408}
pines1600MHz 611 (200x8.0) (128-bit dual-pumped bus)? v PAC611

datos16KB instrucciones256KB 16KB unified L2 on-Area integrada3MB unified L3 *? GB cacheable
? millones0.13μm wide? mm ² area
Itanium 2-1.6G MMX SSE (Deerfield) November, 2004 - {$ 2408}
pines1600MHz 611 (266x6.0) (128-bit dual-pumped bus)? v
PAC611
datos16KB instrucciones256KB 16KB unified L2 on-Area integrada3MB unified L3 *? GB cacheable
? millones0.13μm wide? mm ² area
Itanium
2-9010 MMX SSE (Montecito) (Hyperthreading) 2006?
pines1600MHz 611 (200x8.0) (128-bit dual-pumped bus)? V
PAC611
? KB data? Instrucciones1MB KB unified L2 on-Area integrada6MB unified L3 *? GB cacheable
1720 millones0.09μm ancho? Mm ² area
Itanium 2-9020 MMX SSE (Montecito) (dual coe, Hyperthreading) 2006?
pines1400MHz 611 (200x7.0) (128-bit dual-pumped bus)? V
PAC611
2x? KB datos2x? KB instrucciones2x integrada2x unified 1MB L2 9MB L3 on-unified * Area? GB cacheable
1720 millones0.09μm ancho? mm ² area
Itanium 2-9040 MMX SSE (Montecito) (dual coe, Hyperthreading) 2006?
pines1600MHz 611 (266x6.0) (128-bit dual-pumped bus)? V
PAC611
2x? KB datos2x? KB instrucciones2x integrada2x unified 1MB L2 9MB L3 on-unified * Area? GB cacheable
1720 millones0.09μm ancho? mm ² area
Itanium 2 -?? MMX SSE (Montecito) (dual coe, Hyperthreading) 2006?
611 pin? MHz ("X") (128-bit dual-pumped bus)? V
PAC611
2x? KB datos2x? KB instrucciones2x integrada2x unified 1MB L2 12MB L3 unified on-Area *? GB cacheable
millones0.09μm 1720 wide? mm ² area

Itanium 2 -?? MMX SSE (Fanwood - 2-way) (dual coe, Hyperthreading) 2006?
? pin? MHz ("X") (128-bit dual-pumped bus)? v
?
2x? KB datos2x? KB instrucciones2x? MB L2 unified integrada2x? MB L3 on-Unified Area *? GB cacheable
? million? microns wide? mm ² area

Itanium 2 -?? MMX SSE (Millington - 2-way) (dual coe, Hyperthreading) 2006?
? pin? MHz ("X") (128-bit dual-pumped bus)? v
?
2x? KB datos2x? KB instrucciones2x? MB L2 unified integrada2x? MB L3 on-Unified Area *? GB cacheable
? million? microns wide? mm ² area

Itanium 2 -?? MMX SSE (Shavano) (Hyperthreading) 2006?
? pin? MHz ("X") (128-bit dual-pumped bus)? v
?
? KB data? KB instructions? MB L2 unified or integrated? MB L3 on-Unified Area *? GB cacheable
? million? microns wide? mm ² area

Itanium 2 -?? MMX SSE (Montvale) (dual coe, Hyperthreading) 2006?
? pin? MHz ("X") (128-bit dual-pumped bus)? v
?
2x? KB datos2x? Instrucciones2x KB L2 unified 1MB-12MB on integrada2x Area unified L3 *?
GB cacheable? millones0.065μm ancho? mm ² area
Itanium
3 -?? MMX SSE (Tukwila) (multi coe, Hyperthreading) 2006?
? pines? MHz (-x ?)(?- bit?-pumped bus)? v
?
4x? KB datos4x? KB instrucciones4x? MB L2 unified integrada4x? MB L3 on-unified * Area?
GB cacheable? millones0.065μm ancho? mm ² area
Itanium
3 -?? MMX SSE (Dimona) (dual coe, Hyperthreading) 2006?
? pines? MHz (-x ?)(?- bit?-pumped bus)? v
?
2x? KB datos2x? KB instrucciones2x? MB L2 Unified integrada2x? MB L3 on-Unified Area *? GB cacheable
? million? microns wide? mm ² area
Itanium
3 -?? MMX SSE (Poulson) (multi coe, Hyperthreading) 2006?
? pin? MHz (? x ?)(?- bit?-pumped bus)? v
?
4x? KB datos4x? KB instrucciones4x? MB integrated L2 unified
? million? microns wide? mm ² area



Purple Metal Core Wheel

MICROPROCESSOR TUTORIALS HARDWARE - CHIPS DUAL CORE INTEL XEON



PHOTOS MICROPROCESSOR INTEL XEON DUAL CORE SOCKET FOR
771




INTEL PENTIUM XEON 3200

WITH BUS 800 MHZ


PHOTO-771-SOCKET-LGA




Xeon (Socket 771) Intel Core
No.
pin, bus, multiplied and voltage
L1/L2/L3 Cache Socket

Transistors
Xeon 5030 MMX SSE SSE2 SSE3 (Dempsey) (dual area, Hyperthreading, EM64T, NX bit, VT) May 23, 2006
bolas2666MHz 771 (166x16) (Bus 64 quadpumped bits)? v

Socket 771 2x 16KB data (8-way) 2x 12k μoperaciones (8-way) 2x 2MB L2 unified or integrated (8-way) *?
230 GB cacheable millones0.065μm
ancho206mm ² area Xeon 5050 MMX SSE SSE2 SSE3 (Dempsey) (dual area, Hyperthreading, EM64T, NX bit, VT) May 23, 2006
bolas3000MHz 771 (166x18) (64-bit Bus quadpumped)? v

Socket 771 2x 16KB data (8-way) 2x 12k μoperaciones (8-way) 2x Integrated 2MB unified L2 (8-way) *?
230 GB cacheable millones0.065μm
ancho206mm ² area Xeon 5060 MMX SSE SSE2 SSE3 (Dempsey) (dual area, Hyperthreading, EM64T, NX bit, VT) May 23, 2006
bolas3200MHz 771 (266x12) (64-bit Bus quadpumped)? v

Socket 771 2x 16KB data (8-way) 2x 12k μoperaciones (8-way) 2x 2MB L2 unified or integrated (8-way) *?
230 GB cacheable millones0. 065μm ancho206mm ² area
Xeon 5063 MMX SSE SSE2 SSE3 (Dempsey) (dual area, Hyperthreading, EM64T, NX bit, VT) May 23, 2006
771 bolas3200MHz (266x12) (Bus 64-bit quadpumped)? v
Socket 771
2x 16KB data (8-way) 2x Μoperaciones 12k (8-way) 2x 2MB L2 unified or integrated (8-way) *?
230 GB cacheable millones0.065μm
ancho206mm ² area Xeon 5080 MMX SSE SSE2 SSE3 (Dempsey) (dual area, Hyperthreading, EM64T, NX bit, VT ) May 23, 2006
bolas3733MHz 771 (266x14) (64-bit Bus quadpumped)? v

Socket 771 2x 16KB data (8-way) 2x 12k μoperaciones (8-way) 2x 2MB L2 unified or integrated (8-way) *?
230 GB cacheable millones0.065μm ancho206mm ² area

Intel Core No. of pins, bus, and voltage multiplied
L1/L2/L3 Cache Socket

Transistors
Xeon 5110 MMX SSE SSE2 SSE3 (Woodcrest) (dual coe, EM64T) June 26, 2006
bolas1600MHz 771 (266x6) (64-bit Bus quadpumped)? V

Socket 771 2x 32KB data (8-way) 2x 32KB instruction (8-way) 4MB on-area shared L2 (16 - way) * 64GB cacheable
? millones0.065μm wide? mm ² area
Xeon 5120 MMX SSE SSE2 SSE3 (Woodcrest) (dual coe, EM64T) June 26, 2006
bolas1866MHz 771 (266x7) (64-bit Bus quadpumped)? v

Socket 771 2x 32KB data ( 8-way) 2x 32KB instruction (8-way) 4MB on-area shared L2 (16-way) * 64GB cacheable
? millones0.065μm wide? mm ² area
Xeon 5130 MMX SSE SSE2 SSE3 (Woodcrest) (dual coe, EM64T) June 26, 2006
771 bolas2000MHz (333x6) (64-bit Bus quadpumped)? v

Socket 771 2x 32KB data (8-way) 2x 32KB instruction (8-way) 4MB on-area shared L2 (16-way) * 64GB cacheable
? millones0.065μm wide? mm ² area
Xeon 5140 MMX SSE SSE2 SSE3 (Woodcrest) (dual coe, EM64T) June 26, 2006
bolas2333MHz 771 (333x7) (64-bit Bus quadpumped)? v

Socket 771 2x 32KB data ( 8-way) 2x 32KB instruction (8-way) 4MB on-area shared L2 (16-way) * 64GB cacheable
? millones0.065μm wide? mm ² area
LV Xeon 5148 MMX SSE SSE2 SSE3 (Woodcrest) (dual coe, EM64T) June 26, 2006
bolas2333MHz 771 (333x7) (Bus quadpumped 64-bit)? v

Socket 771 2x 32KB data (8-way) 2x 32KB instruction (8-way) 4MB on-area shared L2 (16-way) * 64GB cacheable
? millones0.065μm wide? mm ² area
Xeon 5150 MMX SSE SSE2 SSE3 (Woodcrest) (dual coe, EM64T) June 26, 2006
bolas2666MHz 771 (333x8) (64-bit Bus quadpumped)? v

Socket 771 2x 32KB data ( 8-way) 2x 32KB instruction (8-way) 4MB on-area shared L2 (16-way) * 64GB cacheable
? millones0.065μm wide? mm ² area
Xeon 5160 MMX SSE SSE2 SSE3 (Woodcrest) (dual coe, EM64T) June 26, 2006
bolas3000MHz 771 (333x9) (64-bit Bus quadpumped)? v

Socket 771 2x 32KB data (8-way) 2x 32KB instruction (8-way) 4MB on-area shared L2 (16-way) * 64GB cacheable
? millones0.065μm wide? mm ² area
SSE SSE2 SSE3 MMX Xeon (Woodcrest) (dual coe, EM64T) 2006? 771
balls? MHz (333X?) (64-bit Bus quadpumped)? V

Socket 771 2x 32KB data (8-way) 2x 32KB instruction (8-way) 4MB on-area shared L2 (16-way) * 64GB cacheable
? millones0.065μm wide? mm ² area

?? MMX SSE SSE2 SSE3 (Tigerton) (quad core, EM64T) 2007? 771
balls? MHz ("X") (64-bit Bus quadpumped)? V

Socket 771 2x 32KB data (8-way) 2x 32KB instruction (8-way) 2x? MB integrated L2 unified (?-Way) * 64GB cacheable
? million? microns wide? mm ² area

?? MMX SSE SSE2 SSE3 (Clovertown) (quad core, dual area, EM64T) 2007? 771
balls? MHz ("X") (64-bit Bus quadpumped)? V

Socket 771 4x 32KB data (8-way) 4x 32KB instruction (8-way) 2x 4MB shared L2 on-Zone (16-way ) * 64GB cacheable
? million? microns wide? mm ² area

?? MMX SSE SSE2 SSE3 (Whitefield) (multi coe, EM64T) 2008? 771
balls? MHz ("X") (64-bit Bus quadpumped)? V

Socket 771? X 32KB data (8-way)? X 32KB instruction (8-way)? MB shared L2 on-Area (?-Way) * 64GB cacheable
? millones0.065μm wide? mm ² area

?? MMX SSE SSE2 SSE3 (Dunnington) (multi coe, EM64T) 2008? 771
balls? MHz ("X") (64-bit Bus quadpumped)? V

Socket 771? X 32KB data (8-way)? X 32KB instruction (8-way)? MB shared L2 on-Zone (? -way) * 64GB cacheable
? million? microns wide? mm ² area

?? MMX SSE SSE2 SSE3 (Harpertown) (8 coe, quad area, EM64T) 2008? 771
balls? MHz ("X") (64-bit Bus quadpumped)? V
Socket 771 8x
32KB data (8-way) 32KB instruction 8x (8-way)? MB shared L2 on-Area (?-Way) * 64GB cacheable
? millones0.045μm wide? mm ² area




Tuesday, May 5, 2009

Cod Liver Oil, Heart Palpitations

TUTORIALS HARDWARE - Pentium D



PHOTOS Intel Pentium D


(SOCKET 775) - TECHNICAL








Intel Pentium D (Socket 775)
Intel Pentium D Processor is a dual-core processor for desktop PCs . It has two separate cores to execute commands on a single processor core físico.Ambos frecuencia.Ambos work on the same processor found within the same structure and are connected to the chipset and memory through the same interface. Multitasking
velocidadGracias all a PC based on Intel Pentium D processor with two cores full processing, you get the flexibility and performance to handle multimedia entertainment, digital photo editing and multiple users simultaneously alike. Your PC gets resources for multitasking, so you can get to accomplish more while running multiple applications, such as editing video while downloading music. Designed for applications
avanzadasObtenga the most out of your demanding multi-threaded applications, perfect for a new world of high-end entertainment. The PC based on Intel Pentium D processor technology with Intel dual-core processing offers the performance to benefit from sophisticated game programs, resulting in realistic game environments and challenging ability to play.
Multiply your multimedia experience Combined with a digital media adapter and a home network, a PC based on Intel Pentium D processor allows two people to share PC content in the same room or even from different parts of the house. For example, a person can check email while the other uses a remote control to access digital photos stored on the same PC and view them on TV lounge
Intel Pentium D (Socket 775)
Core Intel
Number of pins , bus, and voltage multiplied
Cache Socket
L1/L2x

transistors Pentium D-805 MMX SSE SSE2 SSE3 (Smithfield) (dual coe, EM64T, NX bit) February, 2006
bolas2666MHz 775 (133x20) (64-bit Bus quadpumped) Socket T

1.4V 2x 16KB data (8 - way) 2x 12k μoperaciones (8-way) 2x 1MB L2 unified or integrated (8-way) * 4GB cacheable
230 millones0.09μm
ancho206mm ² area D-820 Pentium MMX SSE SSE2 SSE3 (Smithfield) (dual coe, EM64T, NX bit ) May 26, 2005 - {$ 241} 775
bolas2800MHz (200x14) (64-bit Bus quadpumped) Socket T

1.4V 2x 16KB data (8-way) 2x 12k μoperaciones (8-way) 2x 1MB L2 unified or integrated ( 8-way) * 4GB cacheable
millones0.09μm ancho206mm ² 230
area D-830 Pentium MMX SSE SSE2 SSE3 (Smithfield) (dual coe, EM64T, NX bit) May 26, 2005 - {$ 316} 775
bolas3000MHz (200x15) (64-bit Bus quadpumped)
1.4V 2x Socket T
16KB data (8-way) 2x 12k μoperaciones (8-way) 2x 1MB L2 unified or integrated (8-way) * 4GB cacheable
230 millones0.09μm
ancho206mm ² area D-840 Pentium MMX SSE SSE2 SSE3 (Smithfield) (dual coe , EM64T, NX bit) May 26, 2005 - {$ 530} 775
bolas3200MHz (200x16) (64-bit Bus quadpumped) Socket T

1.4V 2x 16KB data (8-way) 2x 12k μoperaciones (8-way) 2x Integrated 1MB unified L2 (8-way) * 4GB cacheable millones0.09μm
230

ancho206mm ² area D-915 Pentium MMX SSE SSE2 SSE3 (Presler) (dual area, EM64T, NX bit) 2H 2006
bolas2800MHz 775 (200x14) (64-bit Bus quadpumped) Socket T

1.3v 2x 16KB data (8 -way) 2x 12k μoperaciones instructions (8-way) 2x 2MB L2 unified or integrated (8-way) *?
376 GB cacheable millones0.065μm
ancho140mm ² area D-920 Pentium MMX SSE SSE2 SSE3 (Presler) (dual area, EM64T , NX bit, VT) February, 2006 - {$ 241} 775
bolas2800MHz (200x14) (64-bit Bus quadpumped) Socket T

1.4V 2x 16KB data (8-way) 2x 12k μoperaciones instructions (8-way) 2x Integrated 2MB unified L2 (8-way) * ? 376 GB cacheable
millones0.065μm
ancho140mm ² area D-925 Pentium MMX SSE SSE2 SSE3 (Presler) (dual area, EM64T, NX bit) [not marketed]
bolas3000MHz 775 (200x15) (64-bit Bus quadpumped) 1.4V Socket T

2x 16KB data (8-way) 2x 12k μoperaciones instructions (8-way) 2x 2MB L2 unified or integrated (8-way) *?
376 GB cacheable millones0.065μm
ancho140mm ² area D-930 Pentium MMX SSE SSE2 SSE3 (Presler) (dual area, EM64T, NX bit, VT) February, 2006 - {$ 316} 775
bolas3000MHz (200x15) (64-bit Bus quadpumped) Socket T

1.4V 2x 16KB data (8-way) 2x μoperaciones 12k instruction (8-way) 2x Integrated 2MB unified L2 (8-way) *?
376 GB cacheable millones0.065μm
ancho140mm ² area D-940 Pentium MMX SSE SSE2 SSE3 (Presler) (dual area, EM64T, NX bit, VT) February, 2006 - {$ 423}
bolas3200MHz 775 (200x16) (64-bit Bus quadpumped) Socket T

1.4V 2x 16KB data (8-way) 2x 12k μoperaciones instructions (8-way) 2x 2MB L2 unified or integrated (8-way) *? GB cacheable 376
millones0.065μm
ancho140mm ² area D-945 Pentium MMX SSE SSE2 SSE3 (Presler) (dual area, EM64T, NX bit) 2H 2006
bolas3400MHz 775 (200x17) (64-bit Bus quadpumped)? v

2x Socket T 16KB data (8-way) 2x 12k μoperaciones instruction (8-way) 2x 2MB L2 unified or integrated (8-way) *?
376 GB cacheable millones0.065μm
ancho140mm ² area D-950 Pentium MMX SSE SSE2 SSE3 (Presler) (dual area, EM64T, NX bit, VT) February, 2006 - {$ 637} 775
bolas3400MHz (200x17) (64-bit Bus quadpumped) Socket T

1.4V 2x 16KB data (8-way) 2x 12k μoperaciones instructions (8-way) 2x 2MB L2 unified or integrated (8 -way) *?
376 GB cacheable millones0.065μm
ancho140mm ² area D-960 Pentium MMX SSE SSE2 SSE3 (Presler) (dual area, EM64T, NX bit, VT) 2H 2006
bolas3600MHz 775 (200x18) (64-bit Bus quadpumped) 1.3v Socket T

2x 16KB data (8-way) 2x 12k μoperaciones instructions (8-way) 2x 2MB L2 unified or integrated (8-way) *?
376 GB cacheable millones0.065μm ancho140mm ² area

Extreme Pentium-840 MMX SSE SSE2 SSE3 (Smithfield ) (dual coe, Hyperthreading, EM64T, NX bit) April 18, 2005 - {$ 999} 775
bolas3200MHz (200x16) (64-bit Bus quadpumped) Socket T

1.4V 2x 16KB data (8-way) 2x 12k μoperaciones (8-way) 2x 1MB L2 unified or integrated (8-way) *?
230 GB cacheable millones0.09μm ancho206mm ² area

Extreme Pentium-955 MMX SSE SSE2 SSE3 (Presler) (dual area, Hyperthreading, EM64T, NX bit, VT) in January, 2006 - {$ 999} 775
bolas3466MHz (266x13) (64-bit Bus quadpumped) Socket T

1.4V 2x 16KB data (8-way) 2x 12k μoperaciones instructions (8-way) 2x 2MB L2 unified or integrated (8-way *)?
376 GB cacheable millones0.065μm ancho140mm ² area

bolas3733MHz 775 (266x14) (64-bit Bus quadpumped) Socket T

1.4V 2x 16KB data (8-way) 2x 12k μoperaciones instructions (8-way) 2x Integrated 2MB unified L2 (8-way) *?
376 GB cacheable millones0.065μm ancho140mm ² area




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